Transistor as Amplifier, Switch and Logic Gates

• Identify NPN and PNP transistor structures and current flow directions
• Analyse the common-emitter (CE) configuration and derive voltage gain
• Use I_C = β I_B to calculate collector current and explain current gain β
• Apply transistor as a switch: saturation (ON) and cut-off (OFF) states
• Construct truth tables for all basic logic gates and identify universal gates
• Apply De Morgan's theorems to simplify Boolean expressions

Level 1 — Foundations

Transistor structure

• NPN: n-type emitter | thin p-type base | n-type collector; conventional current flows from collector to emitter (electrons flow E→C)
• PNP: p-type emitter | thin n-type base | p-type collector; conventional current flows from emitter to collector (holes flow E→C)
• Three terminals: Emitter (E) — heavily doped; Base (B) — very thin, lightly doped; Collector (C) — moderately doped, largest area

Current relationships (CE configuration) $I_E = I_B + I_C$ $I_C = \beta I_B \quad (\beta = h_{FE}, \text{ typically } 50\text{–}300)$ $\alpha = \frac{I_C}{I_E} = \frac{\beta}{\beta + 1} \quad (\alpha < 1, \text{ typically } 0.95\text{–}0.99)$

Common-emitter (CE) configuration

• Input: between base and emitter (V_BE)
• Output: between collector and emitter (V_CE)
• Highest current gain (β) and voltage gain among three configurations
• 180° phase shift between input and output voltage

Logic gates — truth tables

NOT gate: Y = Ā (single input, inverts output)

Level 2 — JEE depth

CE amplifier voltage gain Small-signal voltage gain: $A_V = -\frac{\beta R_C}{r_e} = -\frac{\beta R_C}{r_{in}}$ where r_e = dynamic emitter resistance = V_T/I_E ≈ 25 mV/I_E(mA) ≈ 25 Ω at I_E = 1 mA

The negative sign indicates 180° phase inversion (output is inverted relative to input).

Input and output characteristics

• Input characteristic: I_B vs V_BE (for fixed V_CE) — resembles diode characteristic
• Output characteristic: I_C vs V_CE (for fixed I_B) — three regions:
  • Active region: I_C ≈ β I_B, V_CE > V_CE(sat) — transistor amplifies
  • Saturation region: both junctions forward biased, V_CE ≈ 0.2 V (Si), transistor is fully ON
  • Cut-off region: both junctions reverse biased, I_C ≈ 0, transistor is fully OFF

Transistor as a switch

• Cut-off (OFF state): I_B = 0 → I_C = 0 → V_CE = V_CC (full supply appears across transistor)
• Saturation (ON state): I_B is large enough that transistor is fully ON: V_CE = V_CE(sat) ≈ 0.2 V

Condition for saturation: I_B ≥ I_C(sat)/β = (V_CC − V_CE(sat))/(β × R_C)

Logic gates — Boolean identities and De Morgan's theorems

• De Morgan's theorem 1: $\overline{A+B} = \bar{A} \cdot \bar{B}$ (NOR = AND of inverted inputs)
• De Morgan's theorem 2: $\overline{A \cdot B} = \bar{A} + \bar{B}$ (NAND = OR of inverted inputs)
• NAND as universal gate: NOT (A NAND A), AND (NAND then NOT), OR (NOT each input then NAND)
• NOR as universal gate: NOT (A NOR A), OR (NOR then NOT), AND (NOT each input then NOR)

Why NAND/NOR are called universal gates: any Boolean function can be implemented using only NAND (or only NOR) gates. This is important in digital IC design because a single gate type simplifies manufacturing.

XOR gate $Y = A \oplus B = A\bar{B} + \bar{A}B$ XOR is true when inputs differ. Used in adders, parity checkers, encryption.

JEE traps

• β and α: examiners often give α and ask for β or vice versa. Relationship: β = α/(1−α); α = β/(β+1)
• Voltage gain formula: A_V = −β R_C/r_e — the negative sign is important; do not drop it
• Saturation check: if calculated I_C > V_CC/R_C, transistor is saturated; don't use I_C = β I_B beyond saturation
• De Morgan's: students apply the wrong version; remember "break the bar, change the sign"
• NOR output for (1,0) input: Y = 0 (not 1!) — OR is 1, NOT gives 0

CE amplifier voltage gain

Given: β = 100, R_C = 2 kΩ = 2000 Ω, r_e = 25 Ω (given as dynamic emitter resistance)

Voltage gain:
A_V = −β × R_C / r_e
    = −100 × 2000 / 25
    = −200000 / 25
    = −8000

Answer: Voltage gain = −8000 (magnitude 8000, with 180° phase inversion)

Physical meaning: A 1 mV input signal at the base produces a 8 V output at the
collector — but inverted (input positive peak → output negative peak).
This is why CE amplifiers are called inverting amplifiers.

Note: In practice, gain is limited by supply voltage and biasing; the load line
sets the operating point within the active region.

Transistor switch: minimum base current for saturation

Given: V_CC = 5 V, R_C = 1 kΩ = 1000 Ω, β = 100, V_CE(sat) = 0.2 V

Step 1: Find collector current at saturation
I_C(sat) = (V_CC − V_CE(sat)) / R_C
         = (5 − 0.2) / 1000
         = 4.8 / 1000
         = 4.8 mA

Step 2: Find minimum base current to achieve saturation
I_B(min) = I_C(sat) / β = 4.8 mA / 100 = 0.048 mA = 48 μA

Answer: Minimum I_B = 48 μA to drive transistor into saturation.

For switch design: actual I_B is set 2–5× above I_B(min) to ensure reliable saturation.
If R_B is used: R_B = (V_in − V_BE) / I_B = (5 − 0.7) / (48 × 10⁻⁶) ≈ 89.6 kΩ
Choose R_B ≤ 89 kΩ (e.g., 82 kΩ standard value).

• Q1: A transistor has α = 0.98. Find β and the collector current if I_B = 50 μA.
• Q2: In a CE amplifier, β = 150, R_C = 5 kΩ, I_C = 2 mA. Find r_e and voltage gain.
• Q3: Implement a 3-input OR gate using only 2-input NAND gates. Draw the circuit.
• Q4: For a transistor switch with V_CC = 9 V, R_C = 3 kΩ, β = 50, V_CE(sat) = 0.2 V — find minimum I_B for saturation.
• Stretch: A CE amplifier has I_C = 1 mA at DC bias, R_C = 4.7 kΩ, β = 200, V_CC = 12 V. Find (a) voltage gain, (b) output voltage swing before clipping, (c) maximum input signal amplitude without distortion.

NCERT Chapter 14 link: Sections 14.7–14.10 cover transistor action, CE configuration, transistor as amplifier, transistor as switch, and logic gates. Figures 14.24–14.32 (output characteristics, load line, switch circuit, gate symbols) are essential for JEE. Table 14.2 (truth tables) and Section 14.10.4 (De Morgan's theorems) are standard MCQ sources. NCERT examples 14.5–14.7 directly address CE amplifier calculations.

Exam connections: JEE Main: β from I_B/I_C calculation (1 question per paper), voltage gain MCQ, truth table completion for NAND/NOR/XOR, De Morgan's theorem application. JEE Advanced: load line analysis on output characteristics graph, transistor switch design with R_B calculation, Boolean simplification using De Morgan's theorems, 3–4-variable logic circuit analysis. Universal gate implementation (given circuit, identify overall function) is a favourite JEE Advanced question type.

Study strategy: Master the three operating regions (cut-off, active, saturation) before attempting amplifier or switch problems. For logic gates, write truth tables from scratch for every gate in each practice session — don't memorise, derive. De Morgan's theorems are tested both forwards (simplify expression) and backwards (identify which gate combination equals which function). Practice implementing any gate using only NAND gates — a common JEE Advanced circuit question.

• Use the platform-native live simulation or PhET-style tool for this topic (Circuit Construction Kit — build CE amplifier, vary R_B and observe switching between cut-off, active, and saturation; use logic gate simulator for truth table verification).
• Mirror / body / home activity: think of a light switch as a transistor switch — OFF = cut-off, ON = saturation — and map the transistor switch circuit to the actual wiring in your home.
• Voice or text reflection with AI Mentor: explain to a younger sibling how billions of transistor switches in a phone chip store and process information using just 0s and 1s.

• "Explain how a transistor acts as a switch using an analogy of a water tap or a school gate, to a Class 8 student."
• "What is one common mistake students make when calculating transistor voltage gain, and how would you catch yourself making it?"
• Stretch: "How do billions of transistors in a CPU connect to logic gates, Boolean algebra, and ultimately to running the AI that helps you study? Trace the chain from silicon to software."

• Complete the core practice + one extension activity (photo, table, short reflection, or mini-project) for base XP + topic badge.
• 5-7 day streak or family discussion note = multiplier + visible artifact in parent/principal dashboard.
• Best real-world application stories (anonymised) featured on class or national leaderboard.

• One hands-on project: using the Drishti kit, build a transistor switch circuit (BC547 NPN) that turns an LED ON and OFF based on a base resistor input; measure V_CE in saturation vs cut-off with a multimeter.
• Direct link to Future Skill track: AI Mastery (every AI chip is billions of transistor switches; understanding the switch is foundational to understanding AI hardware), Cyber Defenders (logic gates implement encryption, hashing, and all digital security algorithms at the hardware level).
• Coding extension: write a Python program that takes a Boolean expression as input and generates its truth table; extend to simplify using De Morgan's theorems.

This material emphasises experiential "learning by doing", competency (apply/create/analyse), vocational exposure, critical thinking, and multidisciplinary connections. Designed to feed live worlds, AI Mentor (with memory), gamification, robotics, parent analytics, and future skills — not just exam prep.

Portfolio Evidence Idea: Your photo/table/reflection/project + one sentence on "How this helps me in real life or a possible future path."

Open the Practice tab for aligned questions (easy/medium/hard + case-based) with full AI scaffolding.

See curriculum for cross-links and the full future-skills/robotics chapters.